Samsung details how its 400+ layer V10 NAND is built for AI

Samsung Electronics has offered a closer look at the engineering behind its latest high-density flash memory, explaining how it pushed V-NAND technology beyond the 400-layer mark to address the storage demands created by AI.

The company’s V10 BV-NAND, showcased at FMS 2026 earlier this month, is Samsung’s 10th-generation V-NAND solution. Samsung designed the new generation around the broader requirements of AI workloads, including higher capacity, faster data movement, and improved power efficiency.

Samsung 400+ layer NAND targets the AI era

The growing use of generative AI is changing how storage is used inside data centers. AI systems increasingly need to retain large amounts of intermediate information, including KV cache generated during interactions with large language models. That makes fast, dense, and power-efficient storage increasingly important.

Samsung says its V10 NAND delivers more than 58% higher bit density than the previous generation. It also reaches I/O speeds of at least 4.8Gbps, representing a performance improvement of more than 33%, while cutting power consumption by over 25%.

The company says the technology is not limited to large AI data centers. Its development strategy also considers AI workloads across PCs, smartphones and edge devices.

How Samsung built 400+ layer NAND

Getting beyond 400 layers introduced significant manufacturing challenges. As NAND stacks become taller, issues such as wafer stress, warping and increasingly difficult channel-hole etching become more pronounced.

Samsung addressed these problems through a combination of high-aspect-ratio contact (HARC) etching and wafer bonding. Its HARC Merge approach allows multiple V-NAND structures to be vertically connected, while wafer bonding brings separately manufactured cell and peripheral wafers together.

The company also adopted a Full Capping design to better align the underlying driver circuitry with the cell area while reducing transistor size.